module	rece_send
(
	rst,
	clk,
	cmd,
	din,
	data_done,
	cmd_done,
	dout
);

input	rst;
input	clk;
input	[7:0]	cmd;
input	[31:0]	din;
input	data_done;
input	cmd_done;
output	reg	[31:0]	dout;

reg	[9:0]	din_reg;
reg	[7:0]	cmd_reg;
always@(posedge clk)
begin
	if(!rst)
	begin
		cmd_reg<=0;
	end
	
	else
	begin
		if(cmd_done)
		begin
			cmd_reg<=cmd;
		end
		
		else
		begin
			cmd_reg<=cmd_reg;
		end
	end
end

always@(posedge clk)
begin
	if(!rst)
	begin
		din_reg<=0;
	end
	
	else
	begin
		if(data_done)
		begin
			if(cmd_reg==128)
			begin
				din_reg<=din;
			end
			
			else
			begin
				din_reg<=din_reg;
			end
		end
		
		else
		begin
			din_reg<=din_reg;
		end
	end
end

always@(posedge clk)
begin
	if(!rst)
	begin
		dout<=0;
	end
	
	else
	begin		
		if(cmd_reg==0)	//获取要输出的数据
		begin
			dout<=din_reg;
		end
		
		else
		begin
			dout<=dout;
		end
	end
end

endmodule
